This invention relates to a fault judging device which is for use in simulating a circuit model. Such a fault judging device is particularly useful in a fault simulator.
A conventional fault simulator is implemented by a computer system which is operable in accordance with a predetermined software program. The fault simulator carries out a fault simulation of a circuit model which comprises a plurality of circuit elements. In the fault simulation, one of the circuit elements is selectively enabled at first by a fault data signal indicative of one of the circuit elements in the circuit model. Then, the circuit model is supplied with first through n-th input pattern signals, one by one, representative of first through n-th input patterns where n represents a natural number greater than unity. The first through the n-th input pattern signals are propagated through the circuit model one by one and processed in a processing time duration. As a result, the circuit model produces first through n-th output pattern signals, one by one, representative of first through n-th output patterns which are in one-to-one correspondence to the first through the n-th input patterns.
The fault simulator comprises a fault judging device comprising a pattern memory, such as a magnetic disc device, for memorizing first through n-th normal patterns for defining a normal circuit related to the circuit model. The fault judging device further comprises a comparator connected to the circuit model and the pattern memory for comparing the first through the n-th output patterns with the first through the n-th normal patterns, respectively. When one of the first through the n-th output patterns does not coincide with one of the first through the n-th normal patterns that corresponds to one of the first through the n-th output patterns, the comparator produces a comparison result signal representative of stack fault (Stack at "1" or "0") of one of the circuit elements.
In such a fault simulator, the circuit model is implemented by hardware circuits in order to reduce the processing time duration in the circuit model. However, the fault judging device requires a long time duration in order to carry out comparing operation between the first through the n-th output patterns and the first through the n-th normal output patterns. Furthermore, the fault judging device requires the pattern memory of a large capacity for memorizing first through n-th normal output patterns.